ARM: Is “STMDB SP!, {R0-R8}” (aka PUSH {R0-R8}) an atomic operation?

Question

I wonder if STMDB SP!, {R0-R8} is an atomic operation in ARM(v7), because it looks quite complex to me. So is it for example possible, that the CPU is interrupted somewhere

Answer 1

STM is a single instruction, so it is atomic as much as other instructions. You tell the cpu to save N registers starting from memory pointed by SP-4 then update SP to SP-N*4 in a single instruction. So it is its responsibility to keep things in a consistent state between different mode switches (aka interrupts).