ARM: Is “STMDB SP!, {R0-R8}” (aka PUSH {R0-R8}) an atomic operation?

Question

I wonder if STMDB SP!, {R0-R8} is an atomic operation in ARM(v7), because it looks quite complex to me. So is it for example possible, that the CPU is interrupted somewhere

Answer 1

It is atomic, as far as interrupt handling is concerned.

If I remember correctly, interrupting the instruction causes it to be aborted and re-executed after interrupt processing has finished, in order to guarantee interrupt latency.