Signed multiplication overflow detection in Verilog

Question

Beginner here. I\'m trying to code a simple 16-bit microprocessor in Verilog and implement it on a Spartan 6. The ALU implements all signed operations (no unsigned operation

Answer 1

Just wants to provide an explanation for @Morgan's answer above.

First, it should be noted that in Two's complement representation, no matter how many leading zeros for a positive number or leading ones for a negative number you have, the value is still the same. That is: 1110 is the same as 11110, both are -2.

Now, consider the first overflow example:

  +7 : [0]0111
  +1 : [0]0001 
  +8 : [0]1000

We can see that it we take the carry bit/signed bit of the result, the value is correct in two's complement form (01000 is +8). However, since the result wire can only hold 4 bits, from the hardware perspective, the value is only 1000, which is -8 in two's complement.

Therefore, if we do an XOR on the carry bit and the MSB of the result binary number, we could identify whether the value hardware recognized is the same as the intended, or determine whether overflow happened.