Signed multiplication overflow detection in Verilog

Question

Beginner here. I\'m trying to code a simple 16-bit microprocessor in Verilog and implement it on a Spartan 6. The ALU implements all signed operations (no unsigned operation

Answer 1

That will be failed if you add 7 and -3 for example.

  7 : [0]0111
- 3 : [1]1101
= 4 : [1]0100

The result will show this is underflow however this is not underflow but just +4.