Arithmetic shift acts as a logical shift, regardless of the signed variable

Question

I\'ve got a register declared as so:

logic signed [15:0][2:0][15:0] registers;

When I place a 2\'s compliment number into the array and ari

Answer 1

With Verilog, once you take a part-select, the result is unsigned. Use the $signed system task on the part select to make it signed.

res = $signed(registers[0][0]) >>> 2;