How to define a parameterized multiplexer using SystemVerilog

Question

I am trying to create a module which switches x input data packets to a single output packet according to a one hot input.

If x was a fixed value of 4, I would just

Answer 1

If you can assert that onehot is truly one-hot or 0, then you could use a generate

package mytypes;
typedef logic [7:0] packet_t;
endpackage 

module mux #(int X) (
      input logic [X-1:0] onehot,
      input mytypes::packet_t i_data[X],
      output wire mytypes::packet_t o_data
      );
for(genvar i=0;i