Why do I need to redeclare VHDL components before instantiating them in other architectures?

Question

I\'ve been scratching my head since my first VHDL class and decided to post my question here.

Given that I have a declared entity (and also an architecture of it) an

Answer 1

You can directly instantiate the component, if desired:

  MyInstantiatedEntity : entity work.MyEntity_E
    generic map (
        config          => whatever)
    port map (
        clk             => signal1,
        clk_vid         => signal2,
        ...

Creating a component declaration gives you the extra ability to change what gets bound to the instantiation via a configuration specification or similar.