Verilog: Can you put “assign” statements within always@ or begin/end statements?

Question

Is this allowed?

input w;
     input [8:0]y;
     output reg [8:0]x;
     always@(w)
     begin


     //x[0] or A is never on in any next state
     as         


        

Answer 1

Yes, but you don't want to. Since x[] doesn't depend on x[] the order doesn't matter. Just use <= instead of assign =.