Verilog: Can you put “assign” statements within always@ or begin/end statements?

Question

Is this allowed?

input w;
     input [8:0]y;
     output reg [8:0]x;
     always@(w)
     begin


     //x[0] or A is never on in any next state
     as         


        

Answer 1

Assign is a continuous assignment statement which is used with wires in Verilog. assign statements don't go inside procedural blocks such as always. Registers can be given values in an always block.

Assign statements can be viewed as:

 always @(*)

statements for wires.