Verilog: Can you put “assign” statements within always@ or begin/end statements?

Question

Is this allowed?

input w;
     input [8:0]y;
     output reg [8:0]x;
     always@(w)
     begin


     //x[0] or A is never on in any next state
     as         


        

Answer 1

You can, it's called a "Procedural Continuous Assignment". It overrides ordinary procedural assignments, there doesn't seem to be a call for them in the code you've posted. I'm not sure if they're synthesisable, but I never have cause to use them anyway.

A note on your code - you're missing y from your sensitivity list: eg always @( w or y ) or always @(*) is safer.