better way of coding a D flip-flop

Question

Recently, I had seen some D flip-flop RTL code in verilog like this:

    module d_ff(
            input d,
            input clk,
            input reset,
           


        

Answer 1

As far as simulation is concerned, removing that statement should not change anything, since q should be of type reg (or logic in SystemVerilog), and should hold its value.

Also, most synthesis tools should generate the same circuit in both cases since q is updated using a non-blocking assignment. Perhaps a better code would be to use always_ff instead of always (if your tool supports it). This way the compiler will check that q is always updated using a non-blocking assignment and sequential logic is generated.