I have an input signal from ADC convertor that is 8 bits (std_logic_vector(7 downto 0)
). I have to convert them to a 16 bits signal (std_logic_vector(15 d
With the newly released VHDL-2019 standard you can do
larger_vec <= extend(shorter_vec);
where extend
is a function defined as follows
function extend(vec : std_logic_vector) return target_vec of std_logic_vector is
variable result : std_logic_vector(target_vec'length - 1 downto 0) := (others => '0');
begin
assert vec'length <= target_vec'length report "Cannot extend to shorter vector";
result(vec'length - 1 downto 0) := vec;
return result;
end function;
Tool support is still a bit limited but at least one simulator supports this (Riviera-PRO).