How to convert 8 bits to 16 bits in VHDL?

Question

I have an input signal from ADC convertor that is 8 bits (std_logic_vector(7 downto 0)). I have to convert them to a 16 bits signal (std_logic_vector(15 d

Answer 1

architecture RTL of test is
    signal s8: std_logic_vector(7 downto 0);
    signal s16: std_logic_vector(15 downto 0);
begin
    s16 <= X"00" & s8;
end;