How to convert 8 bits to 16 bits in VHDL?

Question

I have an input signal from ADC convertor that is 8 bits (std_logic_vector(7 downto 0)). I have to convert them to a 16 bits signal (std_logic_vector(15 d

Answer 1

If the 8 bit value is interpreted as signed (2's complement), then the general and standard VHDL conversion method is to use the IEEE numeric_std library:

library ieee;
use ieee.numeric_std.all;

architecture sim of tb is
    signal slv_8  : std_logic_vector( 8 - 1 downto 0);
    signal slv_16 : std_logic_vector(16 - 1 downto 0);
begin
    slv_16 <= std_logic_vector(resize(signed(slv_8), slv_16'length));
end architecture;

So first the std_logic_vector is converted to a signed value, then the resize is applied, which will sign extend the signed value, and the result is finally converted back to std_logic_vector.

The conversion is rather lengthy, but has the advantage that it is general and works even if the target length is changed later on.

The attribute 'length simply returns the length of the slv_16 std_logic_vector, thus 16.

For unsigned representation instead of signed, it can be done using unsigned instead of signed, thus with this code:

    slv_16 <= std_logic_vector(resize(unsigned(slv_8), slv_16'length));