Incrementing Multiple Genvars in Verilog Generate Statement

Question

I\'m trying to create a multi-stage comparator in verilog and I can\'t figure out how to increment multiple genvars in a single generate loop. I\'m trying the following:

Answer 1

Assuming that ci1 has half the depth of tc and you want, say ci1[0] = min(tc[0], tc[1]), ci[1] = min(tc[2], tc[3]) etc, the following should work:

module st_genvar();

  int ci1 [0:127];
  int tc [0:255];

  function int minw(int i1, int i2);
      if(i1 < i2 )
        minw = i1;
      else
        minw = i2;
  endfunction

  genvar i;
  //Level 1
  generate
      for (i=0;i<128;i=i+1)
        begin: level1Comp
            assign ci1[i] = minw(tc[i*2],tc[i*2+1]);
        end
  endgenerate

endmodule