Why can't I increment this `std_logic_vector`

后端 未结 6 1996
萌比男神i
萌比男神i 2020-12-16 15:26

What\'s going on here? Why am I getting an \'operator argument type mismatch\', and what can I do to fix it?

--
-- 32-bit counter with enable and async reset         


        
6条回答
  •  春和景丽
    2020-12-16 15:42

    This will also work:

    nextvalue <= value + '1'; 
    

    Dont know if you are really well versed in VHDL. The following syntax ist logicaly correct if you are using std_logic_arith package

提交回复
热议问题