Passing Generics to Record Port Types

Question

I did recently start to use records for my port definitions, especially if I want to group signals that belong to a certain interface. However, the problem I\'m facing here

Answer 1

Generics in packages is supported in Xilinx's Vivado toolset currently. Ref their document UG901, the section titled "Generics in Packages" for details and a code sample. Need to make sure the source code properties are set up for VHDL-2008, as explained elsewhere in the same document.