Verilog Always block using (*) symbol

Question

I have a simple question regarding how to write an always block in a Verilog module.
If I have the following inputs in my Verilog module:

Answer 1

It's just a shortcut for listing all of the wires that the always block depends on. Those wires are the "sensitivity list". One advantage of using it is that synthesized code is unlikely to care what you put in the sensitivity list (other than posedge and negedge) because the wires will be "physically" connected together. A simulator might rely on the list to choose which events should cause the block to execute. If you change the block and forget to update the list your simulation might diverge from the actual synthesized behavior.