Verilog Always block using (*) symbol

Question

I have a simple question regarding how to write an always block in a Verilog module.
If I have the following inputs in my Verilog module:

Answer 1

The always @(*) syntax was added to the IEEE Verilog Std in 2001. All modern Verilog tools (simulators, synthesis, etc.) support this syntax.

Here is a quote from the LRM (1800-2009):

An incomplete event_expression list of an event control is a common source of bugs in register transfer level (RTL) simulations. The implicit event_expression, @*, is a convenient shorthand that eliminates these problems by adding all nets and variables that are read by the statement (which can be a statement group) of a procedural_timing_ control_statement to the event_expression.

So, your two lines of code may be equivalent (it depends on the code in the body of your always block). However, the @* syntax is easier to maintain.