How can I assign a “don't care” value to an output in a combinational module in Verilog

Question

Imagine we want to describe a combinational circuit that satisfy the following truth table:

a b | s0 s1 s2 s3
-----------------
0 0 |  1  d  d  d
0 1 |  0  1         


        

Answer 1

I would think that supplying x to an output would do the trick -- "unknown" should do exactly what you want. I believe you can wire it directly as an output, but if that's forbidden, you could generate it by wiring both 1 and 0 to the output.