How to 'assign' a value to an output reg in Verilog?

Question

( insert really basic question disclaimer here )

More specifically, I have the following declaration:

output reg icache_ram_rw

And

Answer 1

1. the issue is that the assign statement when sythesized will create the port/pin thats why its need a wire as output .
2. you have created the reg named icache_ram_rw now a register is not same as pin right ....
3. so to assign an register you need to use a proper format of verilog
4. verilog allows the same by using always statement , a DFF is created and the input pin of that DFF would be your icache_ram_rw , the format is already been provided by others .