How to 'assign' a value to an output reg in Verilog?

Question

( insert really basic question disclaimer here )

More specifically, I have the following declaration:

output reg icache_ram_rw

And

Answer 1

Note that you can also assign an initial value to a reg when you declare it, like this:

output reg icache_ram_rw = 1'b0;

This will ensure it starts with the zero value in simulation. For synthesis, your results will depend on the synthesis tool and target technology (for FPGAs, you can generally assign an initial value for hardware; for ASIC, that's not the case).