When must a signal be inserted into the sensitivity list of a process

Question

I am confused about when a signal declared in an architecture must be inserted into the sensitivity list of a process.

Is there is a general law that can be followe

Answer 1

...also, be warned, the sensitivity list has no influence over the behaviour of your design once it is synthesised. It is only used during simulation. Hence it's quite easy to introduce a difference in behaviour between RTL and synthesised code by changes to the sensitivity list.

The rules Josh gives are good, but above all, read the warnings your tools give you and act on them. They normally check that the sensitivity list is correct and will flag any problems. Emacs VHDL mode also has a command to update the sensitivity list, and it's normally pretty good at it.

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Hmmmm, Ninja'd