I am confused about when a signal declared in an architecture must be inserted into the sensitivity list of a process.
Is there is a general law that can be followe
Also, the synthesis tools (talking about the Xilinx XST in this case) don't necessarily always respect the process sensitivity list. If you fail to list all the processes whose values are evaluated in the body of the process, the XST will emit a warning saying that it's going to assume that the signals whose values are evaluated are on the sensitivity list. That may lead to differences between behavioral simulations and actual hardware. Keep it in mind.