What's the difference between parenthesis $() and curly bracket ${} syntax in Makefile?

Question

Is there any differences in invoking variables with syntax ${var} and $(var)? For instance, in the way the variable will be expanded or anything?

Answer 1

There's no difference – they mean exactly the same (in GNU Make and in POSIX make).

I think that $(round brackets) look tidier, but that's just personal preference.

(Other answers point to the relevant sections of the GNU Make documentation, and note that you shouldn't mix the syntaxes within a single expression)