How to wire two modules in Verilog?

前端 未结 3 882
借酒劲吻你
借酒劲吻你 2020-12-12 00:17

I have written two modules DLatch and RSLatch and i want to write verilog code to join those two.

3条回答
  •  感动是毒
    2020-12-12 00:38

    Seriously, you should get yourself a Verilog handbook or search for some online resources.

    Anyway, something like this should work:

    module dff (
        input Clk,
        input D,
        output Q,
        output Qbar
      );
    
      wire q_to_s;
      wire qbar_to_r;
      wire clk_bar;
    
      assign clk_bar = ~Clk;
    
      D_latch dlatch (
        .D(D),
        .Clk(Clk),
        .Q(q_to_s),
        .Qbar(qbar_to_r)
      );
    
      RS_latch rslatch (
        .S(q_to_s),
        .R(qbar_to_r),
        .Clk(clk_bar),
        .Qa(Q),
        .Qb(Qbar)
      );
    
    endmodule
    

提交回复
热议问题