VHDL: How to use CLK and RESET in process

Question

I have written VHDL code for VGA controller for spartan 3E board. The code simulates and works well without the reset and clk process in the code below. But after inserting

Answer 1

You cannot have several drivers for one signal. If you don't have the (clk, reset) process the hcount and vcount signals are each driven by only one process. But when you add the (clk, reset) process it has concurrent drivers.