When to use VHDL library std_logic_unsigned and numeric_std?

Question

I use VHDL-200X in ISE.I always use data type like std_logic_vector,std_logic,integer,boolean and real.Alway

Answer 1

Never use std_logic_arith or std_logic_**signed. Always use numeric_std when signed or unsigned values are needed. The former packages claim to be IEEE, but they aren't. They are vendor specific extensions from Synopsys or Mentor Graphics.

Both defined arithmetic operations on std_logic_vector based on the imported packages. This e.g. means you can't used signed and unsigned values in the same architecture.

Doing all math in integers has some drawbacks:

• no uninitialized value
• no 'X' propagation
• limited to 32 bits
  (How to write a 64 bit counter?)