Target-specific Variables as Prerequisites in a Makefile

Question

I\'m trying to write a GNU make Makefile which has a load of similar targets, where the build commands vary slightly between them. I\'m trying to use target-specific variabl

Answer 1

I've found a rather clean way of side-stepping this limitation. It'd go something like this:

target_1:export special_filename_base=target1_prereq
target_2:export special_filename_base=target2_prereq

some_filename_a = $(special_filename_base).exta
some_filename_b = $(special_filename_base).extb

target_1 target_2:
    $(MAKE) -f $(firstword $(MAKEFILE_LIST)) target-proxy

target-proxy: common_filename $(special_filename_b) $(special_filename_a)
    do_something common_filename --a-weird-option=$(special_filename_a) --second=$(special_filename_b)

Two important points:

1. export the target variables, so that they'll be accessible when we re-run the Makefile.
2. Create a proxy target that has all the original prerequisites of target_1 target_2 and in target_1 target_2 invoke the Makefile again with this proxy target. Since the target specific variables will have values by then (we are in the recipe by that time) and they were exported, they'll be available in target-proxy - voila :)

The downside of this approach is that we are creating another make process - if it's just another one then it's probably ok, but YMMV so be extra careful.