Target-specific Variables as Prerequisites in a Makefile

Question

I\'m trying to write a GNU make Makefile which has a load of similar targets, where the build commands vary slightly between them. I\'m trying to use target-specific variabl

Answer 1

As a simple workaround:

target_1:special_filename=target1_prereq
target_1:target1_prereq
target_2:special_filename=target2_prereq
target_2:target2_prereq

target_1 target_2: common_filename $(special_filename)
    do_something common_filename --a-weird-option=$(special_filename)

There is some redundancy, but it is localized, so it's not too bad.