Target-specific Variables as Prerequisites in a Makefile

Question

I\'m trying to write a GNU make Makefile which has a load of similar targets, where the build commands vary slightly between them. I\'m trying to use target-specific variabl

Answer 1

A target-specific variable is defined only in the target's commands (or in other target-specific assignments); it can't be used as one of the target's prereqs. I don't think there's a clean way to do what you want in Make, but there are several kludgey approaches, such as the following:

EXTENSIONS = .exta .extb
target_1: $(addprefix target1_prereq,$(EXTENSIONS))
target_2: $(addprefix target2_prereq,$(EXTENSIONS))

target_1 target_2: common_filename
    do_something common_filename --a-weird-option=$(filter %.exta,$^) --second=$(filter %.extb,$^)