Append to GNU make variables via command line

Question

I am using a GNU-make Makefile to build a C project with several targets (all, clean, and a few project specific targets). In the process of debugg

Answer 1

There are two ways to pass variables to make:

• Using command line arguments:

  make VAR=value
  

• Using environment:

  export VAR=var; make
  

  or (better because it change environment only for current command)

  VAR=var make
  

They are slightly different. The first one is stronger. It mean you know what you want. The second may be considered like a hint. Difference between them is about operators = and += (without override). These operators are ignored when a variable is defined on command line, but are not ignored when variable is defined in environment. Thus, I suggest you to have a Makefile with:

CC ?= gcc
CFLAGS += -Wall
INTERNAL_VARS = value

and call it with:

CFLAGS=-g make

Notice, if you want to withdraw -Wall, you can use:

make CFLAGS=

Please don't use override keyword, else you won't have any way to change a variable affected with override.