Using wire or reg with input or output in Verilog

Question

When you declare something as input or output, how do you know if you have to also declare it as a reg or a wire?

Answer 1

basically reg is used to store values.For example if you want a counter(which will count and thus will have some value for each count),we will use a reg. On the other hand,if we just have a plain signal with 2 values 0 and 1,we will declare it as wire.Wire can't hold values.So assigning values to wire leads to problems....