What's the difference between conflict miss and capacity miss

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南旧
南旧 2020-12-07 11:49

Capacity miss occurs because blocks are being discarded from cache because cache cannot contain all blocks needed for program execution (program working set is much larger t

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  •  [愿得一人]
    2020-12-07 12:18

    My favorite definition for conflict misses from Reducing Compulsory and Capacity misses by Norman P. Jouppi:

    Conflict misses are misses that would not occur if the cache were fully associative with LRU replacement.

    Let's look at an example. We have a direct-mapped cache of size of 4. The access sequences are

    0(compulsory miss), 1(compulsory miss), 2(compulsory miss), 3(compulsory miss), 4(compulsory miss), 1(hit), 2(hit), 3(hit), 0(capacity miss), 4(capacity miss), 0(conflict miss)

    The second to last 0 is a capacity miss because even if the cache were fully associative with LRU cache, it would still cause a miss because 4,1,2,3 are accessed before last 0. However the last 0 is a conflict miss because in a fully associative cache the last 4 would have replace 1 in the cache instead of 0.

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