Signal temp2 cannot be synthesized, bad synchronous description

Question

entity timer is
    Port ( click : in  STD_LOGIC;
           clear : out  STD_LOGIC;
           t_unlock : out  STD_LOGIC);
end timer;

architecture Behavioral of ti         


        

Answer 1

Your code seems to mix concepts of HDL and "software" languages. I'm not sure what it's supposed to do, but I would refactor it into the code below

architecture Behavioral of timer is
    constant COUNTER_VALUE_TO_REACH_15ns : integer := ;

    signal temp2   : integer range 0 to 20 := 0;
    signal divider : std_logic_vector(7 downto 0) := (others => '0');
begin
    process
    begin
        -- Everything happens when the clock ticks, except for reset
        if rising_edge(click) then
            temp2    <= 0;
            clear    <= '0';
            t_unlock <= '0';

            -- Count how many cycles until we need to increment temp2
            if divider = COUNTER_VALUE_TO_REACH_15ns then
                temp2   <= temp2 + 1;
                divider <= (others => '0'); -- Reset the counter when we reach the required amount of time
            else
                divider <= divider + 1;
            end if;

            if temp2 = 6 then
                clear <= '1';
            elsif temp2 = 20 then
                t_unlock <= '1';
            end if;

        else
        end if;
    end process;
end Behavioral;