Signal temp2 cannot be synthesized, bad synchronous description

Question

entity timer is
    Port ( click : in  STD_LOGIC;
           clear : out  STD_LOGIC;
           t_unlock : out  STD_LOGIC);
end timer;

architecture Behavioral of ti         


        

Answer 1

The VHDL has to follow some synthesis tool specific coding guidelines, for the tool to be able to translate the VHDL code into the FPGA implementation. For implementation to a flip-flop with asynchronous reset, the style can be:

process (clk, rst) is
begin
  -- Clock
  if rising_edge(clk) then
    ... -- Update at clock
  end if;
  -- Asynchronous reset
  if rst = '1' then
    ... -- Update at reset
  end if;
end process;

In the case of your code it looks like you are not using the asynchronous reset, thus the template may be reduced to:

process (clk) is
begin
  if rising_edge(clk) then
    ... -- Update at clock
  end if;
end process;

The exercise is now for you to fit your code into that template, and unfortunately it is pretty hard to determine the exact intention based on the provided code.