Is process in VHDL reentrant?

Question

Is it possible two or more sequential run for a process in VHDL?

What will happen if another event happen (on sensitivity signal list) while the sequen

Answer 1

When starting out using VHDL (or any other HDL for that matter), it is hugely important to discard all notions of sequential code, and instead focus on the flow of data through the hardware. In hardware, everything is inherently parallel (everything happens simultaneously), but uses constantly changing data (input signals) to calculate constantly changing results (output signals)!

Without going into more advanced topics such as variables, wait commands etc., everything within a process happens simultaneously. If conflicting things occur within the same process (multiple writes to the same signal), the last statement in the process wins, which is often where confusion about "sequential" code in VHDL comes from.

This works due to the way that values are assigned to signals. When assigning a value to a signal, the value of the signal does not immediately change! Instead, the assigned value is remembered and will be committed as the actual signal value later (in preparation for the next delta cycle, which is effectively the next quantum of time).

Since the next delta cycle will not begin until all processes from the previous delta cycle have completed, signal values will only change when no process is running. Once all signals have changed, the next delta cycle begins and any process sensitive to one of the changed signals will be executed.

If a process is sensitive to a signal it also writes, you have what is known as a combinatorial loop, e.g., a gate where the output feeds an input. This is (almost) always an error in your circuit, and will usually cause simulators to enter an infinite delta-cycle loop.

That's all I'll write for now, as Brian Drummond's answer just popped up as I was writing this, but feel free to leave a comment and I'll add some more details.