Can anyone help me to create a Verilog testbench?

Question

Can anyone help me create a testbench or just the input code for my following code? I\'m using XILINX.

module fsmb (input rst,clk,a,
             output reg          


        

Answer 1

Xilinx ISE will generate a skeleton test fixture automatically. Go to menu item Project->New Source. The dialog box will ask you to "Select Source Type" click "Verilog Test Fixture" and give it a name like testbench1 and click Next. Then it will then ask you which module in your project to associate with it. Select fsmb. Click Next and Finish.

You still have to tweak the testbench like setting the initial input values, generating a clock, and lifting reset after a few clocks.