I\'m working on a FIR filter, specifically the delay line. x_delayed
is initialized to all zeros.
type slv32_array is array(natural range <&g
the reason you have a problem is that the logic thinks you have two things assigning into the same signal simultaneously - both the continues assignment and the register assignment loop. keep with the register implementation.
edit
if you have modelsim, you can use the 'trace x' option and see where it comes from.
might be that the other simulator also have this feature, but for modelsim i'm certain it works