VHDL Variable Vs. Signal

Question

I have been reading a text (Don\'t have it in front so can\'t give the title) about VHDL programming. One problem I\'ve been having a hard time understanding from the text i

Answer 1

Variables - they are local to a process, their value is updated as soon as the variable gets a new value.

Shared Variables- are like variables but they can be accessed from different processes.

Signals- Their scope is bigger, every process can access signals declared in the architecture or a specific block( if there is). There value updates after the process is suspended or encounters a wait statement.