VHDL Variable Vs. Signal

Question

I have been reading a text (Don\'t have it in front so can\'t give the title) about VHDL programming. One problem I\'ve been having a hard time understanding from the text i

Answer 1

On a side note variables can't just live in processes (but also e.g. in procedures), furthermore they can be shared variables accessible from multiple processes (see: http://www.ics.uci.edu/~jmoorkan/vhdlref/var_dec.html).