VHDL Variable Vs. Signal

Question

I have been reading a text (Don\'t have it in front so can\'t give the title) about VHDL programming. One problem I\'ve been having a hard time understanding from the text i

Answer 1

variables: Temporary location; they are used to store intermediate values within "process".

signals: Update signal values. Run process activated by changes on signal.While process is running all signals in system remain unchanged.

Differences:

variables: They are local; no delay; declared within process

signals: They are global (before begin); delay due to wire; declared before key word begin