VHDL Variable Vs. Signal

Question

I have been reading a text (Don\'t have it in front so can\'t give the title) about VHDL programming. One problem I\'ve been having a hard time understanding from the text i

Answer 1

Variables are intended to be a used for storing a value within a process. As such It's scope is limited. There tends to be a less direct relationship to synthesized hardware.

Variables also get a value immediately, whereas signals don't. the following two processes have the same effect:

signal IP, NEXTP : STD_LOGIC_VECTOR(0 to 5);

process (CLK)
    Variable TEMP : STD_LOGIC_VECTOR(0 to 5);
    begin
        if (rising_edge(clk)) then
            TEMP := IP;
            IP <= NEXTP;
            NEXTP <= TEMP(5) & TEMP(0 to 4);
        end if;
end process;

---

signal IP, NEXTP : STD_LOGIC_VECTOR(0 to 5);

process (CLK)

    begin
        if (rising_edge(clk)) then
            IP <= NEXTP;
            NEXTP <= IP(5) & IP(0 to 4);
        end if;
end process;

This is because the updates get scheduled, but haven't actually changed yet. the <= includes a temporal element.