VHDL Variable Vs. Signal

Question

I have been reading a text (Don\'t have it in front so can\'t give the title) about VHDL programming. One problem I\'ve been having a hard time understanding from the text i

Answer 1

Variables are used when you want to create serialized code, unlike the normal parallel code. (Serialized means that the commands are executed in their order, one after the other instead of together). A variable can exist only inside a process, and the assignment of values is not parallel. For example, consider the following code:

signal a,b : std_logic_vector(0 to 4);

process (CLK)
    begin
        if (rising_edge(clk)) then
            a <= '11111';
            b <= a;
        end if;
end process;

will put into b the value of a before the process ran, and not '11111'. On the other hand, the code:

signal a,b : std_logic_vector(0 to 4);

process (CLK)
    variable var : std_logic_vector(0 to 4);
    begin 
        if (rising_edge(clk)) then
            var := '11111';
            a <= var;
            b <= var;
        end if;
end process;

will put the value '11111' into both a and b.

Frankly, in my experience, most of the time you don't need to use variables, the only place I used it was in a loop where I needed to check if any of a number of signals is 1:

type    BitArray        is array (natural range <>) of std_logic;

--...

entity CAU_FARM is
    port
        (
            --   IN   --
              REQUEST         : in BitArray(0 to (FLOW_num -1));
              --..
        );
end CAU_FARM;
--...

farm_proc: process(CLK_FARM, RESET)
    variable request_was_made_var : std_logic;
    begin
    if RESET = C_INIT then 
       -- ...

    elsif rising_edge(CLK_FARM) then

            -- read state machine --
        case read_state is
            when        st_read_idle =>

                request_was_made_var := '0';
                for i in 0 to (FLOW_num -1) loop
                    if (REQUEST(i) = '1') then
                        request_was_made_var := '1';
                    end if;
                end loop;
                if (request_was_made_var = '1') and (chosen_cau_read_sig /= 8) then
                    read_state <= st_read_stage_1;
                    for i in 0 to (FLOW_num -1) loop
                        if (i = choice_out_sig) then
                            ACKNOWLEDGE(i) <= '1';
                        end if;
                    end loop;
                else
                    read_state <= st_read_idle;
                end if;
            ------------------------
            when        st_read_stage_1 =>
            --...