Error adding std_logic_vectors

Question

I wanna have a simple module that adds two std_logic_vectors. However, when using the code below with the + operator it does not synthesize.

library IEE         


        

Answer 1

Good advice from @Aurelien to use numeric_std.

Bear in mind that adding two 32 bit values can result in a 33 bit value and decide how you want to handle the overflow.