Error adding std_logic_vectors

Question

I wanna have a simple module that adds two std_logic_vectors. However, when using the code below with the + operator it does not synthesize.

library IEE         


        

Answer 1

Don't use std_logic_arith - I've written about this (at some length :).

Do use numeric_std - and do use the right type on your entity ports. If you are doing arithmetic, use numerical types (either integers, or (un)signed vectors, as appropriate). They'll synthesise perfectly well.

std_logic_vectors are good for

• when you don't care about numerical values (a set of control bits, some random data bits)
• when you don't know about the type of the input (say an adder which can operate on both signed and unsigned numbers based on a control flag).