How does a zero register improve performance?

Question

In the MIPS ISA, there\'s a zero register ($r0) which always gives a value of zero. This allows the processor to:

1. Any instruction which produces r

Answer 1

A zero register allows saving some opcodes when designing a new instruction set architecture (ISA).

For example, the main RISC-V spec has 32 pseudo-instructions that depend on the zero register (cf. Tables 26.2 and 26.3). A pseudo-instruction is an instruction that is mapped by the assembler to another real instruction (for example, branch-if-equal-to-zero is mapped to branch-if-equal). For comparison: the main RISV-V spec lists 164 real instruction opcodes (i.e. counting RV(32|64)[IMAFD] base/extensions, a.k.a. RV64G). That means without a zero register RISC-V RV64G would occupy 32 more opcodes for those instructions (i.e. 20 % more). For a concrete RISC-V CPU implementation, this real-to-pseudo instruction ratio may shift in either direction depending on which extensions are selected.

Having less opcodes simplifies the instruction decoder.

A more complex decoder needs more time for decoding instructions or occupies more gates (that can't be used for more useful CPU units) or both.

Existing, incrementally developed ISAs have to deal with backwards-compatibility. Thus, if your original ISA design doesn't include a zero register, you can't just add it in a later revision without breaking compatibility. Also, if your existing ISA already requires a very complex decoder, adding then a zero register doesn't pay off.

Besides the modern RISC-V ISA (developed since 2010, first ratification in 2019), ARMv8 AArch64 (a 64 Bit ISA released in 2011), in contrast to the previous ARM 32 bit ISAs, also features a zero register. Because of this and other changes AArch64 ISA has much less in common with previous ARM 32 Bit ISAs than - say - x86 and x86-64 ISAs.

In contrast to AArch64, x86-64 doesn't has a zero register. Although x86-64 is more modern than the previous 32 bit x86 ISA, its ISA only changed incrementally. Thus, it features all the existing x86 opcodes plus 64 bit variants, and thus the decoder already is very complex.