packed vs unpacked vectors in system verilog

Question

Looking at some code I\'m maintaining in System Verilog I see some signals that are defined like this:

node [range_hi:range_lo]x;

and other

Answer 1

bit a [3:0] -> unpacked array The unpacked array cannot be used as a[0]='b1, it has to be used as full a={8{'b1}}

---> in above statement a[0] ='b1; will work for unpacked array , it won't work where some portion of the unpkd arry[eg logic unpkd [8];] like unpkd = 5'h7; assignment same will work for pkd array --> unpkd = unpkd +2; won't wok for unpkd will work for pkd