packed vs unpacked vectors in system verilog

Question

Looking at some code I\'m maintaining in System Verilog I see some signals that are defined like this:

node [range_hi:range_lo]x;

and other

Answer 1

Unpacked arrays will give you more compile time error checking than packed arrays.

I see unpacked arrays on the port definitions of modules for this reason. The compiler will error if the dimensions of the signal are not exactly the same as the port with unpacked arrays. With packed arrays it will normally just go ahead and wire things the best it can, not issuing an error.