packed vs unpacked vectors in system verilog

Question

Looking at some code I\'m maintaining in System Verilog I see some signals that are defined like this:

node [range_hi:range_lo]x;

and other

Answer 1

bit[3:0] a -> packed array The packed array can be used as a full array (a='d1) or just part of an array (a[0]='b1)

bit a [3:0] -> unpacked array The unpacked array cannot be used as a[0]='b1, it has to be used as full a={8{'b1}}